ADE5166 datasheet(116/148 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 116 of 148

RTC REGISTERS

Table 126. RTC Register List

Address

RTCPTR[4:0]

Mnemonic

R/W

Length

Signed/

Unsigned

Default

Value

Description

0x00

Reserved

N/A

Reserved.

0x01

HTHSEC

R/W

This counter updates every 1/128 second, referenced from

the calibrated 32.768 kHz clock. It overflows from 127 to 00,

incrementing the seconds counter, SEC.

0x02

SEC

R/W

This counter updates every second, referenced from the

calibrated 32.768 kHz clock. It overflows from 59 to 00,

incrementing the minutes counter, MIN

0x03

MIN

R/W

This counter updates every minute, referenced from the

calibrated 32.768 kHz clock. It overflows from 59 to 00,

incrementing the hours counter, HOUR

0x04

HOUR

R/W

This counter updates every Hour, referenced from the

calibrated 32.768 kHz clock. It overflows from 23 to 00,

incrementing the DAY and DATE counters.

0x05

DAY

R/W

This counter updates every day, referenced from the

calibrated 32.768 kHz clock. It overflows from 6 to 0

0x06

DATE

R/W

This counter updates every day, referenced from the

calibrated 32.768 kHz clock. It overflows from 28/29/30 or 31

to 01, depending on the month, incrementing the month

counter, MONTH.

0x07

MONTH

R/W

This counter starts at 1 and updates every month, referenced

from the calibrated 32.768 kHz clock. It overflows from 12 to

01, incrementing the year counter, YEAR.

0x08

YEAR

R/W

This counter updates every year, referenced from the

calibrated 32.768 kHz clock.

0x09

INTVAL

R/W

The interval timer counts according to the timebase

established in the ITS[1:0] bits of the RTC Configuration SFR

(TIMECON, 0xA1). Once the number of counts is equal to

INTVAL, the ITFLAG flag is set and a pending RTC interrupt is

created if enabled. Note that the interval counter is 8-bits so

it could count up to 255 sec, for example.

0x0A

AL_SEC

R/W

Alarm second register. When this register matches the SEC

all other enabled alarms match their corresponding timekeep-

ing register. If enabled, a pending RTC interrupt is generated.

0x0B

AL_MIN

R/W

Alarm minute register. When this register matches the MIN

all other enabled alarms match their corresponding timekeep-

ing register. If enabled, a pending RTC interrupt is generated.

0x0C

AL_HOUR

R/W

Alarm hour register. When this register matches the HOUR

other enabled alarms match their corresponding timekeep-

ing register. If enabled, a pending RTC interrupt is generated.

0x0D

AL_DAY

R/W

Alarm day register. When this register matches the DAY

all other enabled alarms match their corresponding timekeep-

ing register. If enabled, a pending RTC interrupt is generated..

0x0E

AL_DATE

R/W

Alarm date register. When this register matches the DATE

all other enabled alarms match their corresponding timekeep-

ing register. If enabled, a pending RTC interrupt is generated.

0x0F

RTC_CAL

R/W

Configuration of the RTC calibration output (see Table 127).

0x10

XTALOS

R/W

Temperature offset for crystal temperature compensation

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