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ADL5592ACPZ-R7 Datasheet(PDF) 13 Page - Analog Devices

Part # ADL5592ACPZ-R7
Description  250 MHz to 2400 MHz RF Variable Gain Amplifier
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADL5592ACPZ-R7 Datasheet(HTML) 13 Page - Analog Devices

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ADL5592
Rev. 0 | Page 13 of
20
1
0
1
0
1
0
t0
t1
t3
t2
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE.
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL LATCHES
ON LE FALLING EDGE.
D0
D9
LE
CLK
DATA
Figure 19. Timing Diagram of SPI Port Transmission
Table 4. 10-Bit Gain Words for SPI Port
ATTN 2
ATTN 1
Resulting Attenuation
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ATTN 1 (dB)
ATTN 2 (dB)
Total Attenuation (dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
2
2
0
0
1
0
0
0
0
0
0
0
0
4
4
0
1
0
0
0
0
0
0
0
0
0
8
8
1
0
0
0
0
0
0
0
0
0
0
16
16
1
1
1
1
1
0
0
0
0
0
0
31
31
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
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0
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1
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2
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2
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1
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4
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1
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8
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8
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0
1
0
0
0
0
16
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16
0
0
0
0
0
1
1
1
1
1
31
0
31
1
1
1
1
1
1
1
1
1
1
31
31
62
Table 5. Timing Requirements for the SPI Port
Mnemonic
Description
Min
Max
Unit
t0
Latch enable setup time. Time between latch enable active (high) and first rising edge of serial clock.
15
ns
t1
Serial data setup time. Time between valid serial data and rising clock edge. Note that this time applies
to all bits in the serial data stream
15
ns
t2
Serial data hold time. Time after rising clock edge during which the serial data line cannot change in
value. Note that this time applies to all bits in the serial data stream
15
ns
t3
Latch enable hold time. Time after final falling clock edge during which the latch enable must remain
active (high).
15
ns
fCLK
Clock period.
15
MHz



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