AT89S53_00 datasheet(29/33 Pages) ATMEL

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AT89S53

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Notes:

1. AC Inputs during testing are driven at V

CC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measure-

ments are made at V

IH min. for a logic 1 and VIL max.

for a logic 0.

Float Waveforms(1)

Notes:

1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded V

OH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V

CC = 4.0V to 6V and Load Capacitance = 80 pF

Symbol

Parameter

12 MHz Oscillator

Variable Oscillator

Units

Min

Max

Min

Max

XLXL

Serial Port Clock Cycle Time

1.0

12t

CLCL

µs

QVXH

Output Data Setup to Clock Rising

Edge

700

10t

CLCL - 133

XHQX

Output Data Hold after Clock Rising

Edge

CLCL - 117

tXHDX

Input Data Hold after Clock Rising

Edge

XHDV

Clock Rising Edge to Input Data

Valid

700

10t

CLCL - 133

AT89S53 Datasheet(PDF) 29 Page - ATMEL Corporation

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