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STD3NM50 Datasheet(PDF) 1 Page - STMicroelectronics

Part # STD3NM50
Description  N-CHANNEL 500V - 2.5ohm - 3A DPAK/IPAK Zener-Protected MDmesh™ Power MOSFET
PDF  10 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STD3NM50 Datasheet(HTML) 1 Page - STMicroelectronics

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April 2003
STD3NM50
STD3NM50-1
N-CHANNEL 500V - 2.5
Ω - 3A DPAK/IPAK
Zener-Protected MDmesh™Power MOSFET
s
TYPICAL RDS(on) = 2.5 Ω
s
HIGH dv/dt AND AVALANCHE CAPABILITIES
s
IMPROVED ESD CAPABILITY
s
LOW INPUT CAPACITANCE AND GATE
CHARGE
s
LOW GATE INPUT RESISTANCE
s
TIGHT PROCESS CONTROL AND HIGH
MANUFACTORING YIELDS
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain pro-
cess with the Company’s PowerMESH™ horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar completition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increase
the power density of high voltage converters allow-
ing system miniaturization and higher efficiencies.
ABSOLUTE MAXIMUM RATINGS
(•)Pulse width limited by safe operating area
TYPE
VDSS
RDS(on)
ID
STD3NM50
STD3NM50-1
500V
500V
<3
Ω
<3
Ω
3A
3A
Symbol
Parameter
Value
Unit
VDS
Drain-source Voltage (VGS =0)
500
V
VDGR
Drain-gate Voltage (RGS =20kΩ)
500
V
VGS
Gate- source Voltage
±30
V
ID
Drain Current (continuous) at TC = 25°C
3A
ID
Drain Current (continuous) at TC = 100°C
1.89
A
IDM (q)
Drain Current (pulsed)
12
A
PTOT
Total Dissipation at TC = 25°C
46
W
VESD(G-S)
Gate source ESD(HBM-C=100pF, R=15K
Ω)
4KV
Derating Factor
0.37
W/°C
dv/dt(1)
Peak Diode Recovery voltage slope
15
V/ns
Tstg
Storage Temperature
–65 to 150
°C
Tj
Max. Operating Junction Temperature
150
°C
(1)ISD<3A, di/dt<400A/µs, VDD<V(BR)DSS,TJ<TJMAX
1
3
DPAK
TO-252
3
2
1
IPAK
TO-251
INTERNAL SCHEMATIC DIAGRAM


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