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DR80390CPU Datasheet(PDF) 1 Page - Digital Core Design |
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DR80390CPU Datasheet(HTML) 1 Page - Digital Core Design |
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1 / 7 page ![]() All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. D DR R8 80 03 39 90 0C CP PU U High Performance 8-bit Microcontroller ver 3.10 OVERVIEW DR80390CPU is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories . The core has been designed with a special concern about low power consump- tion . Additionally an advanced power man- agement unit makes DR80390CPU core per- fect for portable equipment where low power consumption is mandatory. DR80390CPU soft core is 100% binary- compatible with the industry standard 80C390 & 8051 8-bit microcontroller. There are two configurations of DR80390CPU: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR80390CPU has RISC architecture 6.7 times faster com- pared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR80390CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES ● 100% software compatible with industry standard 80390 & 8051 ○ LARGE mode – 8051 instruction set ○ FLAT mode – 80390 instruction set ● RISC architecture enables to execute in- structions 6.7 times faster compared to standard 8051 ● 12 times faster multiplication ● 9.6 times faster division ● Up to 256 bytes of internal (on-chip) Data Memory ● Up to 16M bytes of contiguous Program Memory ● Up to 16M bytes of external (off-chip) Data Memory ● User programmable Program Memory Wait States solution for wide range of memories speed ● User programmable External Data Memory Wait States solution for wide range of memories speed ● De-multiplexed Address/Data bus to allow easy connection to memory ● Interface for additional Special Function Registers |
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