AT91SAM7S128-AI datasheet(21/32 Pages) ATMEL

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AT91SAM7S128 Summary Preliminary

6116AS–ATARM–20-Oct-04

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Vectoring

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Optimizes interrupt service routine branch and execution

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One 32-bit vector register per interrupt source

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Interrupt vector register reads the corresponding current interrupt vector

•Protect Mode

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Easy debugging by preventing automatic operations

•Fast Forcing

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Permits redirecting any interrupt source on the fast interrupt

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General Interrupt Mask

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Provides processor synchronization on events without triggering an interrupt

Debug Unit

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Comprises:

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One two-pin UART

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One Interface for the Debug Communication Channel (DCC) support

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One set of Chip ID Registers

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One Interface providing ICE Access Prevention

•Two-pin UART

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Implemented features are compatible with the USART

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Programmable Baud Rate Generator

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Parity, Framing and Overrun Error

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Automatic Echo, Local Loopback and Remote Loopback Channel Modes

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Debug Communication Channel Support

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Offers visibility of COMMRX and COMMTX signals from the ARM Processor

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Chip ID Registers

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Identification of the device revision, sizes of the embedded memories, set of

peripherals

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Chip ID is 0x270c0740 (VERSION 0)

Periodic Interval Timer

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20-bit programmable counter plus 12-bit interval counter

Watchdog Timer

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12-bit key-protected Programmable Counter running on prescaled SCLK

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Provides reset or interrupt signals to the system

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Counter may be stopped while the processor is in debug state or in idle mode

Real-time Timer

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32-bit free-running counter with alarm running on prescaled SCLK

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Programmable 16-bit prescaler for SLCK accuracy compensation

PIO Controller

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One PIO Controller, controlling 32 I/O lines

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Fully programmable through set/clear registers

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Multiplexing of two peripheral functions per I/O line

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For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

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Input change interrupt

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Half a clock period glitch filter

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Multi-drive option enables driving in open drain

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