DS80C320-END datasheet(71/175 Pages) DALLAS

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High-Speed Microcontroller User’s Guide

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TWO CYCLE INSTRUCTION TIMING Figure 5-4

Example: ANL A, direct:

55h addr7-0

*Shaded areas are held in a weak latch on the port until overdriven.

THREE CYCLE INSTRUCTIONS

Three cycle instructions come in two varieties. The first requires three memory accesses. These are

similar to one and two cycle instructions in that the number of bytes equals the number of cycles.

The second variety is a three cycle instruction that simply requires 12 clocks to perform the function.

This may have one or two bytes. Examples of both types are shown below.

ANL direct, #data

53h

(3 bytes)

a 7–a 0

d7–d0

SJMP rel

80h

(2 bytes)

a 7–a 0

INC DPTR

A3h

(1 byte)

In the first example, the first memory fetch is the opcode. The second is the location of the destination

memory accesses, so it requires three machine cycles. The second example has the operand in the first

byte and the jump location in the second. It requires three cycles to actually perform the jump. The third

example contains simply the opcode, which is one byte. This instruction involves the manipulation of a

16-bit register so it takes longer than 8-bit operations. Figure 5-5 shows the timing of all three types of

three cycle instructions.

CLK

ALE

PSEN

AD0-

POR

A7-0

PIC

RETURN

DATA

ADDRESS

A15-A8

INSTRUCTION

FETCH

OPERAND

FETCH

ADDRESS

A15-A8

A7-0

PC+1

RETURN DATA OPER

AND ADDRESS 7-0

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