STLC5432 datasheet(22/46 Pages) STMICROELECTRONICS

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When DEL is at ”0”, Bit 0 of TS0

is indicated by the rising edge of Frame

synchronization signal.

When DEL is at ”1”, Bit 0 of TS0 is delayed;

the rising edge of Frame Synchronization

indicates the bit located just before Bit 0

Time Slot 0.

AVT

Adaptative Voltage Threshold Validation.

When AVT is at 1, the adaptive voltage

threshold is validated.

When AVT = 0, the adaptive function is not

validated; receiving is performed if the

attenuation of the signal is less than 6 dB.

EQV

Equalizer Validation.

When EQV is at ”1” internal equalizer is

validated (external capacitors are required

at the LI1 and LI2 inputs).

When EQV is at 0, the equalizer is never

operating (external capacitors are not

required).

TABLE OF DIFFERENT LOCAL MULTIPLEX (with Parallel microprocessor interface only)

CONFIGURATION BITS

Local Clock

Multiplexes

DIN

DOUT

DCP

LCLK in kHz

Data Rate in Kb/s

Number of Time

Slots (TS)

Time Slot in

accordance with

the TSn of the

device 0

≤ n ≤ 31

2048

4096

2048

1 X 32

TSn

4096

8192

4096

2 X 32

TS 2n

4096

8192

TS 2n + 1

8192

16384

8192

4 X32

TS 4n

8192

16384

TS 4n + 1

8192

16384

TS 4n + 2

8192

16384

TS 4n + 3

Ex : M2 = 1, M1 = 1, M0 = 0, each Multiplex includes 128 Time Slots, the data processed by the de-

vice during the internal time Slot 3 are the data connecte d to multiplexes during the external time slot

14 = 4 X 3 + 2.

STLC5432

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