Features modification

SPEAR-09-H042

4/16

2

Features modification

To fit the new small package a number of features has been reduced or limited:

●

Analog to digital converter (ADC)

●

eASIC GPIOs

●

External FPGA emulation mode

●

Dynamic RAM data path

●

UARTs

2.1

Analog to digital converter (ADC)

ADC feature has been completely deleted so the 16 analog channels, the related test

output, the power balls and the reference voltages have been removed.

2.2

eASIC GPIOs

SPEAR-09-H022 features 112 GPIOs in the eASIC customizable part, some of these I/Os

have been removed, but 87 are still available on SPEAR-09-H042.

Unusable hidden eASIC GPIOs (74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100-111)

must be configured as inputs.

2.3

External FPGA emulation mode

SPEAR-09-H022 has the capability to emulate the internal eASIC behavior with an external

FPGA through the component GPIOs. This feature has been completely removed on

SPEAR-09-H042 hence the developement boards must use the 420 PBGA components.

2.4

Dynamic RAM data path

The SPEAr component features a multi purpose memory controller to interface SDRAM or

DDR memories able to work with different data path widths.

While SPEAR-09-H022 handles 8 and 16-bit DDRs or 8, 16 and 32-bit SDRAMs, on

SPEAR-09-H042 to save 16 data balls and the related "data mask" balls, the SDRAM data

path has been limited to 16-bit like the DDR one.

2.5

UARTs

Two of the original UART interfaces have been removed, SPEAR-09-H042 features just the

UART1 interface.