M48T212V_07 datasheet(9/35 Pages) STMICROELECTRONICS

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M48T212V

Operation

9/35

Operation

Automatic backup and write protection for an external SRAM is provided through VOUT,

E1CON and E2CON pins. (Users are urged to ensure that voltage specifications, for both the

SUPERVISOR chip and external SRAM chosen, are similar). The SNAPHAT® containing

the lithium energy source used to permanently power the real-time clock is also used to

retain RAM data in the absence of VCC power through the VOUT pin.

The chip enable outputs to RAM (E1CON and E2CON) are controlled during power transients

to prevent data corruption. The date is automatically adjusted for months with less than 31

days and corrects for leap years (valid until 2100). The internal watchdog timer provides

programmable alarm windows.

The nine clock bytes (Fh-9h and 1h) are not the actual clock counters, they are memory

locations consisting of BiPORT™ READ/WRITE memory cells within the static RAM array.

Clock circuitry updates the clock bytes with current information once per second. The

information can be accessed by the user in the same manner as any other location in the

static memory array.

Byte 8h is the clock control register. This byte controls user access to the clock information

and also stores the clock calibration setting. Byte 7h contains the watchdog timer setting.

The watchdog timer can generate either a reset or an interrupt, depending on the state of

the Watchdog Steering Bit (WDS). Bytes 6h-2h include bits that, when programmed, provide

for clock alarm functionality.

Alarms are activated when the register content matches the month, date, hours, minutes,

and seconds of the clock registers. Byte 1h contains century information. Byte 0h contains

additional flag information pertaining to the watchdog timer, alarm and battery status.

The M48T212V also has its own Power-Fail Detect circuit. This control circuitry constantly

monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance,

the circuit write protects the TIMEKEEPER® register data and external SRAM, providing

data security in the midst of unpredictable system operation. As VCC falls below VSO, the

control circuitry automatically switches to the battery, maintaining data and clock operation

until valid power is restored.

2.1

Address decoding

The M48T212YV accommodates 4 address lines (A3-A0) which allow access to the sixteen

bytes of the TIMEKEEPER clock registers. All TIMEKEEPER registers reside in the

SUPERVISOR chip itself. All TIMEKEEPER registers are accessed by enabling E (Chip

Enable).

M48T212V Datasheet(PDF) 9 Page - STMicroelectronics