STA559BWQS datasheet(37/66 Pages) STMICROELECTRONICS

37 / 66 page

STA559BWQS

37/66

5.5

Configuration register E (addr 0x04)

5.5.1

Max power correction variable

Table 36.

Max power correction variable

5.5.2

Max power correction

Table 37.

Max power correction

Setting the MPC bit turns on special processing that corrects the STA50x power device at

high power. This mode should lower the THD + N of a full DDX system at maximum power

output and slightly below. If enabled, MPC is operational in all output modes except tapered

(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-

out channels.

5.5.3

Noise-shaper bandwidth selection

Table 38.

Noise-shaper bandwidth selection

SVE

ZCE

DCCV

PWMS

AME

NSBW

MPC

MPCV

Bit

RST

Name

Description

0RW

MPCV

Max power correction variable:

0: Use standard MPC coefficient

1: Use MPCC bits for MPC coefficient

Bit

RST

Name

Description

1RW

MPC

Max power correction: setting of 1 enables power

bridge correction for THD reduction near maximum

power output.

Bit

RST

Name

Description

NSBW

Noise-shaper bandwidth selection:

1 - 3rd order NS

0 - 4th order NS

STA559BWQS Datasheet(PDF) 37 Page - STMicroelectronics

STA559BWQS Datasheet(HTML) 37 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL