SPEAR-09-P022 datasheet(7/40 Pages) STMICROELECTRONICS

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SPEAR-09-P022

Product overview

7/40

Product overview

An outline picture of the main SPEAr Plus600 functional interfaces is shown in Figure 1.

Figure 1.

Main SPEAr Plus600 functional interfaces

1.1

Features

The following main functionalities are implemented in the SPEAr Plus600 SoC device:

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Dual ARM926EJ-S core @333 MHz, 16 Kbyte-I/D cache, configurable TMC-I/D size,

MMU, TLB, JTAG and ETM trace module (multiplexed interfaces)

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600 Kbyte reconfigurable logic array (programmable through 4 Metal and 4 Vias)

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128 Kbyte configurable internal memory pool (single and dual port memory)

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32 Kbyte ROM (code customizable) 8 Kbyte common SRAM

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Dynamic power save features

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High performance linked list 8 channels DMA

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Ethernet GMII/MII (IEEE802.3/3x/1Q), management i/f

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USB2.0 device (high-full speed), integrated PHY transceiver

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2-USB2.0 host (high-full-low speed), integrated PHY transceiver

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Ext. memory i/f: 8/16-bit DDR1@200 MHz/DDR2@333 MHz

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Flash interface: nand 8/16-bit and serial (up to 50 Mbps)

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3-SPI master/slave (motorola-texas-national) up to 40 Mbps

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I2C (high-fast-slow speed) master/slave

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2-UART (speed rate up to 460.8 Kbps)

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IrDA (Fir-Mir-Sir) from 9.6 Kbps to 4 Mbps speed-rate

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Color LCD up to 1024x768 resolutions, 24 bpp true colour, STN/TFT display panel

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10 GPIOs bidirectional signals with interrupt capability

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9 LVDS (8 out and 1 input) signals, customizable interface through programmable logic

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88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks)

SPEAr Plus600

GMII/MII

USB2.0 dev

USB2.0 host(2)

CLCD

DDR 1/2

PL_GPIOs

PL_LVDSs

JTAG & Test

I2C

SPIs (3)

UARTs (2)

IrDA

GPIOs

ADCs

Flash Serial

Flash Nand

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