Data Brief

For further information contact your local STMicroelectronics sales office.

April 2008

Rev 1

1/5

5

STA2062A

Cartesio™ family

infotainment application processor with embedded GPS

Features

– Cache: 16 Kbyte instruction, 16 Kbyte data

– 8 Kbyte instruction TCM (tightly coupled

memory)

– 8 Kbyte data TCM

– 32 Kbyte embedded ROM for boot

– Two banks of 64 Kbyte embedded SRAM

– 512 Byte embedded SRAM for back-up

– 4 Gbyte total linear address space

– Memory extension through:

Flexible static memory controller-FSMC

(NOR/NAND Flash, CF/CF+, ROM, SRAM

support)

Mobile DDR/SDRAM controller:

16 bit data @166 MHz, 2 Chip Select,

512 Kbit each

– 64-channel interrupt controller (VIC)

– 16-vectorized interrupts with 16

programmable priority level

– Two 8-channel double port system DMA

controllers

– 32 DMA request for each controller

– Two external DMA requests are supported

embedded subsystem

input capture/output compare and PWM

64x12 receive FIFO with DMA and hardware

flow control

separate transmit and receive FIFO with

Motorola-SPI, National-MICROWIRE and

Texas- SSI support modes

separate transmit and receive FIFO

panels

(ULPI interface)

integrated 1.1 physical layer transceiver

interface (SD/SDIO/MMC) up to 8 bit data

embedded medium trace module

2.5 V ±10%

– LFBGA16x16x1.4 mm (19x19 balls)

– 0.8 mm ball pitch, (0.4 mm ball)

– Full array

Table 1.

Device summary

Order code

Package

Packing

STA2062A

LFBGA361

Tray

LFBGA361 (16x16x1.4mm)

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