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STW5095 Datasheet(PDF) 46 Page - STMicroelectronics |
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STW5095 Datasheet(HTML) 46 Page - STMicroelectronics |
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46 / 73 page  STw5095 Control interface and master clock 45/72 Figure 8. Control interface: SPI format timing tDDO tDDOL tDDOF SPIOHIZ=0 SPIOHIZ=1 tSCSF tHSCK tLSCK tSDI tHDI tSCSR tHICS SDIN SDO SCLK CSB 15 8 0 W/R D7 D7 D0 D0 tPSCK tHCS Table 3. Control interface timing with SPI format Symbol Parameter Test Condition Min. Typ. Max. Unit tHICS CSB pulse width high 80 ns tSCSR Setup time CSB rising edge to SCLK rising edge 20 ns tSCSF Setup time CSB falling edge to SCLK rising edge 20 ns tHCS Hold time CSB rising edge from SCLK rising edge 20 ns tSDI Setup time SDIN to SCLK rising edge 20 ns tHDI Hold time SDIN from SCLK rising edge 20 ns tDDOF SDO first Delay time from SCLK falling edge 30 ns tDDO SDO Delay time from SCLK falling edge 20 ns tDDOL SDO Delay time from CSB rising edge 30 ns tPSCK Period of SCK 100 ns tHSCK SCK pulse width high Measured from VIH to VIH 40 ns tLSCK SCK pulse width low Measured from VIL to VIL 40 ns |
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