STPIC44L02 datasheet(12/21 Pages) STMICROELECTRONICS

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STPIC44L02

12/21

Figure 12 : 8-Bit Serial Programming Example (two predrivers cascated)

Figure 13 : Fault Reading Example

PARALLEL INPUT DATA OPERATION

In addition to the serial interface the STPIC44L02

also

provides

parallel

interface

the

microcontroller. The output turns on when either

the parallel or the serial interface make it turn on.

The parallel data terminals are real time control

inputs for the outputs drivers. SCLK and CS are

not required to transfer parallel input data to the

output buffer. Fault data must be read over the

serial data bus as described in the serial data

operation section of this datasheet (see figure 13).

The parallel input must be transitated low and then

high to clear and reenable a gate output after it

has been disabled due to a shorted load fault

condition.

CHIPSET

PERFORMANCE

UNDER

FAULT

CONDITIONS

The STPIC44L02 and power FET arrays are

designed for normal operation over a battery

voltage range of 8V to 24V with load fault

detection from 4.8V to 34V. It offers onboard fault

detection to handle a variety of faults that may

occur within a system. The circuits primary

function is to prevent damage to the load and the

power FETs in the event that a fault occurs.

Note that unused DRAIN0-DRAIN3 inputs must

be connected to VBAT through a pull-up resistor to

prevent

false

reporting

open

load

fault

conditions. The circuitry detects the fault, shuts off

the output to the FET and reports the fault to the

microcontroller.

The

primary

faults

under

consideration are:

1) Shorted Load

2) Open Load

3) over battery voltage shutdown

4) Under battery voltage shutdown.

SHORTED LOAD FAULT CONDITION

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