33291L datasheet(17/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33291L

FUNCTIONAL DESCRIPTION

FAULT LOGIC OPERATION

INTRODUCTION

The MCU can perform a parity check of the fault logic

operation by comparing the command 8-bit word to the status

8-bit word. Assume after system reset, the MCU first sends

an 8-bit command word to the 33291L. This word is called

Command Word 1. Each output to be turned ON will have its

corresponding data bit low. Refer to the data transfer timing

illustration in Figure 17.

As Command Word 1 is being written into the Shift register

of the 33291L, a status word is being simultaneously written

and received by the MCU. However, the word being received

by the MCU is the status of the previous write word to the

33291L, Status Word 0. If the command word of the MCU is

written a second time (Command Word 2 = Command Word

1), the word received by the MCU, Status Word 2, is the

status of Command Word 1. The timing diagram illustrated in

Figure 17 depicts this operation. Status Word 2 is then

compared with Command Word 1. The MCU will Exclusive

OR Status Word 2 with Command Word 1 to determine if the

two words are identical. If the two words are identical, no

faults exist. The timing between the two write words must be

greater than 100

μs to receive proper drain status. The

system data bus integrity may be tested by writing two like

words to the 33291L within a few microseconds of each

other.

INITIAL SYSTEM SETUP TIMING

The MCU can monitor two kinds of faults:

1. Communication errors on the data bus

2. Actual faults of the output loads

After initial system startup or reset, the MCU will write one

word to the 33291L. If the word is repeated within

approximately five microseconds of the first word, the word

received by the MCU, at the end of the repeated word, serves

as a confirmation of data bus integrity (1). At startup, the

33291L will take 25

μs to 100 μs before a repeat of the first

word should be repeated at least 100

μs later to verify the

status of the outputs.

The SO of the 33291L will indicate any one of four faults.

The four possible faults are:

1. Overtemperature

2. Output OFF Open Fault

3. Short Fault (overcurrent)

4. VPWR Overvoltage Fault

With the exception of the Overvoltage Fault, all of these

faults are output specific. Overtemperature Detect, Output

OFF Open Detect, and Output Short Detect are dedicated to

each output separately such that the outputs are independent

in operation. A VPWR Overvoltage Detect is of a global nature,

causing all outputs to be turned OFF.

OVERTEMPERATURE FAULT

Patent pending Overtemperature Detect and shutdown

circuits are specifically incorporated for each individual

output. The shutdown following an Overtemperature

condition is independent of the system clock or any other

logic signal. Each independent output shuts down at 155°C

to 185°C. When an output shuts down due to an

Overtemperature Fault, no other outputs are affected. The

MCU recognizes the fault since the output was commanded

to be ON and the status word indicates it is OFF. A maximum

hysteresis of 20°C ensures an adequate time delay between

output turn OFF and recovery. This avoids a very rapid turn

ON and turn OFF of the device around the Overtemperature

threshold. When the temperature falls below the recovery

level for the Overtemperature Fault, the device will turn ON

only if the Command Word during the next write cycle

indicates the output should be turned ON.

OVERVOLTAGE FAULT

An Overvoltage condition on the VPWR pin causes the

33291L to shut down all outputs until the overvoltage

condition is removed and the device is re-programmed by the

SPI. The overvoltage threshold on the VPWR pin is specified

as 28 V to 36 V with 1.0 V typical hysteresis. Following the

overvoltage condition, the next write cycle sends the SO pin

the hexadecimal word $FF (all ones), indicating all outputs

are turned OFF. In this way, potentially dangerous timing

problems are avoided and the MCU reset routine ensures an

orderly startup of the loads. The 33291L does not detect an

overvoltage on the VDD pin. Other external circuitry, such as

the Motorola 33161 Universal Voltage Monitor, is necessary

to accomplish this function.

OUTPUT OFF OPEN LOAD FAULT

An Output OFF Open Load Fault is the detection and

reporting of an open load when the corresponding output is

disabled (input bit programmed to a logic high state). To

understand the operation of the Open Load Fault detect

circuit, see Figure 18. The Output OFF Open Load Fault is

detected by comparing the drain voltage of the specific

MOSFET output to an internally generated reference. Each

output has one dedicated comparator for this purpose.

33291L Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

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