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M24128-BFMB3TP Datasheet(PDF) 26 Page - STMicroelectronics

Part # M24128-BFMB3TP
Description  128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM
PDF  39 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24128-BFMB3TP Datasheet(HTML) 26 Page - STMicroelectronics

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DC and AC parameters
M24128, M24C64, M24C32
26/39
Table 17.
AC characteristics (M24xxx-W6, M24xxW3, M24xxR6)
Test conditions specified in Table 8 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tXH1XH2
(1)
1.
Values recommended by the I²C-bus Fast-Mode specification.
tR
Input signal rise time
20
300
ns
tXL1XL2
(1)
tF
Input signal fall time
20
300
ns
tDL1DL2
tF
SDA (out) fall time
20
100
ns
tDXCX
tSU:DAT Data in set up time
100
ns
tCLDX
tHD:DAT Data in hold time
0
ns
tCLQX
tDH
Data out hold time
200
ns
tCLQV
(2)(3)
2.
To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3.
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 5).
tAA
Clock low to next data valid (access time)
200
900
ns
tCHDX
(4)
4.
For a reStart condition, or following a Write cycle.
tSU:STA Start condition set up time
600
ns
tDLCL
tHD:STA Start condition hold time
600
ns
tCHDH
tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
Write time
5(5)
5.
For production lots assembled from 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R
(1.8 V to 5.5 V range) memories are specified with tW = 5 ms (instead of 10ms).
ms



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