MSC7118 datasheet(43/60 Pages) FREESCALE

43 / 60 page

Hardware Design Considerations

MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7

Freescale Semiconductor

3.2.2.3

Case 3

The power-up sequence is as follows:

Turn on the VDDIO (3.3 V) supply first.

Turn on the VDDC (1.2 V) supply second.

Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third).

Note:

Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.

The power-down sequence is as follows:

Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first).

Turn off the VDDC (1.2 V) supply second.

Turn of the VDDIO (3.3 V) supply third (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.

•

Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for

power-up and power-down.

•

Refer to Figure 28 for relative timing for Case 3.

Figure 28. Voltage Sequencing Case 3

Time

Ramp-down

Ramp-up

VDDIO = 3.3 V

VDDM = 2.5 V

VDDC = 1.2 V

VREF = 1.25 V

<10 ms

MSC7118 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc