HD151011

Rev.2.00, Jul.16.2004, page 2 of 13

Function Table

Control Inputs

CLR

PR

SPE

SPE

SPE

SPE

C/

TTTT

Mode

Operation Description

H

H

H

X

Generally count

Down count at the rise edge of clock (CLK)

Down count at the fall edge of clock (

CLK)

X

X

L

X

Synchronous preset

Jn data is preset at the rise of clock (CLK), the fall of clock

(

CLK)

—

—

—

H

—

Clock inputs (CLK,

CLK) is CMOS level

—

—

—

L

—

Clock inputs (CLK,

CLK) is TTL level

L

H

—

—

Initialize of Q output

Initialize of Q = “L”

H

L

—

—

Initialize of Q output

Initialize of Q = “H”

Note:

1. Synchronous preset (

SPE) input can set max 99 down counts.

2. When the count value is 0, the next clock pulse presets the data to invert the output.

3. CLR and PR inputs initialize output state.

4. Clock inputs (CLK,

CLK) is selectable CMOS level (V

C/

T, PR, CLR and SPE inputs are CMOS level)

Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB)

H :

High level

L

:

Low level

X :

Immaterial

— :

Irrespective of condition

Pin Arrangement

15

16

17

18

1

2

3

4

5

6

7

14

CO

GND

(Top view)

8

13

19

20

J 0

(Test 1)

J 1

J 2

J 3

J 4

J 5

J 6

9

10

J 7

12

11

(Test 2)

C / T

CLK

CLK

Q

PR

SPE

CLR

*

*