HD49340F/HF

Rev.1.0, Apr 20, 2004, page 19 of 22

Operation Sequence at Power On

RESET bit

RESET = "Low"

(RESET mode)

OBP

High-speed pulse is the right phase

OBP is the right phase

SPBLK

SPSIG

ADCLK

etc.

OBP is started within this period

HD49340F/HF

serial data transfer

RESET = "High"

(RESET cancellation)

Must be stable within the operating

power supply voltage range

Start control

of TG and

camera DSP

(1) Register 2 setting

(2) Register 2 setting

(3) Register 0 and 1 settings

(4) Please perform an offset calibration in the period which avoided PBLK of V.

: Set all bits in register 2 to the usage condition, and set the RESET bit to low.

: Cancel the RESET mode by setting the register 2 RESET bit to high.

Do not change other register 2 settings. Offset calibration starts automatically.

: After the offset calibration is terminated, set registers 0 and 1.

(2) Register 2 setting

(1) Register 2 setting

(3) Registers 0

and 1 settings

0 ms

or more

1 ms or more

2 ms or more

2 ms or more

Prohibition

period

Ends after

40000 clock cycles

Automatic offset

calibration

The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10.

(4)Offset calibration

(automatically starts

after RESET

cancellation)