Rev.3.00, Jul.15.2005, page 1 of 7

HD74LS195A

4-bit Parallel-Access Shift Register

REJ03D0457–0300

Rev.3.00

Jul.15.2005

This 4-bit register features parallel inputs, parallel outputs, J-

K serial inputs, shift / load control input, and a direct

overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of

operation:

• Parallel (broadside) load

• Shift (in the direction Q

Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data

is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During

loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high.

Serial data for this mode is entered at the J-

K inputs. These inputs permit the first stage to perform as a J-K, D-, or T-

type flip-flop as shown in the function table.

Features

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LS195AFPEL

SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

EL (2,000 pcs/reel)

Pin Arrangement

(Top view)

GND

15

16

1

2

3

4

5

6

7

14

8

9

10

11

12

13

Clear

J

D

Shift/Load

C

A

K

CK

Clear

J

K

A

B

C

D

Shift/Load

Clock

B

Outputs

Parallel

Inputs

Serial

Inputs