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M306V2EEFS Datasheet(PDF) 120 Page - Renesas Technology Corp |
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M306V2EEFS Datasheet(HTML) 120 Page - Renesas Technology Corp |
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120 / 271 page  Rev.1.40 Oct 06, 2004 page 120 of 269 M306V2ME-XXXFP, M306V2EEFP <UART0> • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) <UART0> • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 2.11.23 Typical transmit/receive timings in UART mode Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi CTSi The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. “1” “0” “1” “L” “H” “0” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • CTS function is disabled. • Transmit interrupt cause select bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 SP ST P SP D0 D1 ST Stopped pulsing because transmit enable bit = “0” Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Data is set in UARTi transmit buffer register D0 D1 D2 D3 D4 D5 D6 D7 ST SP D8 D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 ST SPSP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register. “0” SP Cleared to “0” when interrupt request is accepted, or cleared by software |
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