M66288FP datasheet(21/24 Pages) RENESAS

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M66288FP

REJ03F0156-0310 Rev.3.10 Apr.04.2008

Page 21 of 23

N-bit Delay 2

(Sliding timings of WRES and RRES at a cycle corresponding to delay length)

Reset cycle

0 cycle

1 cycle

2 cycle

n-1 cycle

Reset cycle

tRESS tRESH

tDS tDH

tAC

tOH

tDS tDH

n cycle

0 cycle

n+1 cycle

1 cycle

n+2 cycle

2 cycle

n+3 cycle

3 cycle

Delay length n

tRESS tRESH

WCK

RCK

WRES

(0)

(1)

(2)

(n-1)

(n+1)

(n+2)

(n+3)

(n)

(1)

(3)

RRES

(0)

(n-2)

(2)

·····Write side

·····Read side

262144

≥ n ≥ 16

WE, RE = "L"

N-bit Delay 3

(Sliding address by disabling RE at a cycle corresponding to delay length)

Reset cycle

0 cycle

1 cycle

2 cycle

n-1 cycle

tRESS tRESH

tDS tDH

tAC

tOH

tDS tDH

n cycle

0 cycle

n+1 cycle

1 cycle

n+2 cycle

2 cycle

n+3 cycle

3 cycle

Delay length n

tNREH tRES

WCK

RCK

WRES

(0)

(1)

(2)

(n-1)

(n+1)

(n+2)

(n+3)

(n)

(1)

(3)

RRES

(0)

(n-2)

(2)

·····Write side

·····Read side

262144

≥ n ≥ 16

WE = "L"

HIGH-Z

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