HD404618TF datasheet(60/91 Pages) RENESAS

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HD404618 Series

Table 27 LCD Control Register

LCR

Bit 2

Display in

Watch Mode or

Subactive Mode Bit 1

Power Switch

On/Off

Bit 0

Blank/Display

Off

Blank

Display

Note:

When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator

as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the

LCD clock, always set bit 2 of the LCR to 0.

LCD Duty/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display

duty and LCD clock source, as shown in table 28.

Table 28 LCD Duty/Clock Control Register

LMR

Bit 3

Bit 2

Bit 1

Bit 0

Duty Selection/Input Clock Selection

—

1/4 duty cycle

—

1/3 duty cycle

—

1/2 duty cycle

—

Static

—

CL0 (32.768/64 kHz when using 32.768-kHz oscillator)

—

CL1 (f

cyc/256)

—

CL2 (f

cyc/2048)

—

CL3 (refer to table 29)

Note: f

cyc is the divided system clock output.

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