4524 datasheet(64/161 Pages) RENESAS

64 / 161 page

Rev.2.00

Jul 27, 2004

page 64 of 159

REJ03B0091-0200Z

4524 Group

• Program counter (PC) ..........................................................................................................

Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE) ..................................................................................................

• Power down flag (P) .............................................................................................................

• External 0 interrupt request flag (EXF0) ..............................................................................

• External 1 interrupt request flag (EXF1) ..............................................................................

• Interrupt control register V1 ..................................................................................................

• Interrupt control register V2 ..................................................................................................

• Interrupt control register I1 ...................................................................................................

• Interrupt control register I2 ...................................................................................................

• Interrupt control register I3 ...................................................................................................

• Timer 1 interrupt request flag (T1F) .....................................................................................

• Timer 2 interrupt request flag (T2F) .....................................................................................

• Timer 3 interrupt request flag (T3F) .....................................................................................

• Timer 4 interrupt request flag (T4F) .....................................................................................

• Timer 5 interrupt request flag (T5F) .....................................................................................

• Watchdog timer flags (WDF1, WDF2) ..................................................................................

• Watchdog timer enable flag (WEF) ......................................................................................

• Timer control register PA ......................................................................................................

• Timer control register W1 .....................................................................................................

• Timer control register W2 .....................................................................................................

• Timer control register W3 .....................................................................................................

• Timer control register W4 .....................................................................................................

• Timer control register W5 .....................................................................................................

• Timer control register W6 .....................................................................................................

• Clock control register MR .....................................................................................................

• Serial I/O transmit/receive complation flag (SIOF) ..............................................................

• Serial I/O mode register J1 ..................................................................................................

• Serial I/O register SI .............................................................................................................

• A/D conversion completion flag (ADF) .................................................................................

• A/D control register Q1 .........................................................................................................

• A/D control register Q2 .........................................................................................................

• A/D control register Q3 .........................................................................................................

• Successive approximation register AD ................................................................................

• Comparator register ..............................................................................................................

• LCD control register L1 ........................................................................................................

• LCD control register L2 ........................................................................................................

“✕” represents undefined.

Fig. 50 Internal state at reset

(2) Internal state at reset

Figure 50 and 51 show internal state at reset (they are the same af-

ter system is released from reset). The contents of timers, registers,

flags and RAM except shown in Figure 50 are undefined, so set the

initial value to them.

000

(Interrupt disabled)

000

(Prescaler stopped)

(Timer 1 stopped)

(Timer 2 stopped)

(Timer 3 stopped)

(Timer 4 stopped)

(Timer 5 stopped)

(Timer LC stopped)

100

(External clock selected,

serial I/O port not selected)

✕✕✕

000

✕✕✕

000

111

✕✕

✕✕✕

✕✕

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