HD74ACT161/HD74ACT163

Rev.2.00, Jul.16.2004, page 2 of 8

Logic Symbol

PE

TC

CEP

CET

CP

MR for HD74ACT161

SR for HD74ACT163

*

Pin Names

CEP

Count Enable Parallel Input

CET

Count Enable Trickle Input

CP

Clock Pulse Input

MR (HD74ACT161)

Asynchronous Master Reset Input

SR (HD74ACT163)

Synchronous Reset Input

P

Parallel Data Inputs

PE

Parallel Enable Input

Q

Flip-Flop Outputs

TC

Terminal Count Output

Functional Description

The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to

state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the

Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-to-

High transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence:

asynchronous reset (HD74ACT161),

synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste (

MR,

HD74ACT161), Synchronous Reset (

SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and

Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode Select Table. A Low signal on

MR overrides all other inputs and asynchronously forces all outputs Low. A Low signal on SR overrides counting and

parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on

PE overrides counting

and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP.

With

PE and MR (HD74ACT161) or SR (HD74ACT163) High, CEP and CET permit counting when both are High.

Conversely, a Low signal on either CEP or CET inhibits counting.

The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the

SR, PE, CEP and CET

inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with

respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter

is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET

inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is

therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.

Logic Equations: Count Enable = CEP•CET•

PE

TC = Q