SH7145 datasheet(73/930 Pages) RENESAS

Part #	SH7145

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

PDF	930 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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73 / 930 page

2. CPU

Rev.4.00 Mar. 27, 2008 Page 29 of 882

REJ09B0108-0400

2.4.3

Instruction Format

The instruction formats and the meaning of source and destination operand are described below.

The meaning of the operand depends on the instruction code. The symbols used are as follows:

• xxxx: Instruction code

• mmmm: Source register

• nnnn: Destination register

• iiii: Immediate data

• dddd: Displacement

Table 2.9

Instruction Formats

Source

Operand

Destination

Operand

Example

0 format

xxxx

—

NOP

—

nnnn: Direct

MOVT

Control register or

system register

nnnn: Direct

STS

MACH,Rn

n format

xxxx

nnnn

Control register or

system register

nnnn: Indirect pre-

decrement register

STC.L SR,@-Rn

mmmm: Direct

Control register or

system register

LDC

Rm,SR

m format

xxxx

mmmm

xxxx

mmmm: Indirect

post-increment

Control register or

system register

LDC.L @Rm+,SR

mmmm: Indirect

—

JMP

@Rm

mmmm: PC relative

using Rm

—

BRAF

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