SH7203 datasheet(86/1686 Pages) RENESAS

Part #	SH7203

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1686 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

86 / 1686 page

Section 2 CPU

Rev. 2.00 Apr. 16, 2008 Page 56 of 1652

REJ09B0313-0200

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

The 20-bit immediate data (imm) for the MOVI20

instruction is sign-extended.

Sign-

extended

imm (20 bits)

—

Immediate

#imm:20

The 20-bit immediate data (imm) for the MOVI20S

instruction is shifted by eight bits to the left, the

upper bits are sign-extended, and the lower bits are

padded with zero.

Sign-extended

imm (20 bits) 00000000

31 27

—

#imm:8

The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions is zero-extended.

—

#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions is sign-extended.

—

#imm:8

The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.

—

#imm:3

The 3-bit immediate data (imm) for the BAND, BOR,

BXOR, BST, BLD, BSET, and BCLR instructions

indicates the target bit location.

—

SH7203 Datasheet(PDF) 86 Page - Renesas Technology Corp

SH7203 Datasheet(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL