M30281FAHP datasheet(73/423 Pages) RENESAS

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7. Clock Generation Circuit

page 53

)

(

7.3 On-chip Oscillator Clock

This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU

and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock

for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer

to 10.3 Count source protective mode, Watchdog Timer).

The on-chip oscillator after reset oscillates. The on-chip oscillator clock f2(ROC) divided by 16 is used for

the CPU clock. It can also be turned off by setting the CM21 bit in the CM2 register to “0” (main clock or PLL

clock). If the main clock stops oscillating when the CM20 bit in the CM2 register is “1” (oscillation stop, re-

oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation detection

interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the micro-

computer.

7.4 PLL Clock

The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the

clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL

frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is

used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the

CM11 bit in the CM1 register to “1”.

Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main

clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”

(PLL stops). Figure 7.10 shows the procedure for using the PLL clock as the clock source for the CPU.

The PLL clock frequency is determined by the equation below.

PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits PLC0 register

(However, 10 MHz

≤ PLL clock frequency ≤ 24 MHz in M16C/28B, 10 MHz ≤ PLL clock frequency ≤ 20

MHz in M16C/28)

The PLC02 to PLC00 bits can be set only once after reset. Table 7.2 shows the example for setting PLL

clock frequencies.

XIN

(MHz)

PLC02

PLC01

PLC00

Multiplying factor

PLL clock

(MHz)(1)

001

010

Table 7.2 Example for Setting PLL Clock Frequencies

NOTE:

1. 10 MHz

≤ PLL clock frequency ≤ 24 MHz in M16C/28B, 10 MHz ≤ PLL clock frequency ≤ 20 MHz in

M16C/28.

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