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HD64F3687G Datasheet(PDF) 21 Page - Renesas Technology Corp |
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HD64F3687G Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 536 page  Rev.5.00 Nov. 02, 2005 Page xxi of xxxii Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3687 Group of F-ZTAT TM and Mask-ROM Versions.............................................................................................. 3 Figure 1.2 Internal Block Diagram of H8/3687N (EEPROM Stacked Version) ............................ 4 Figure 1.3 Pin Arrangement of H8/3687 Group of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A) ......................................................................................................... 5 Figure 1.4 Pin Arrangement of H8/3687N (EEPROM Stacked Version) (FP-64E)....................... 6 Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 12 Figure 2.1 Memory Map (2) ......................................................................................................... 13 Figure 2.1 Memory Map (3) ......................................................................................................... 14 Figure 2.2 CPU Registers ............................................................................................................. 15 Figure 2.3 Usage of General Registers .........................................................................................16 Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 17 Figure 2.5 General Register Data Formats (1).............................................................................. 19 Figure 2.5 General Register Data Formats (2).............................................................................. 20 Figure 2.6 Memory Data Formats................................................................................................. 21 Figure 2.7 Instruction Formats...................................................................................................... 32 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 36 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 39 Figure 2.11 CPU Operation States................................................................................................ 40 Figure 2.12 State Transitions ........................................................................................................ 41 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address........................................................................................................ 42 Section 3 Exception Handling Figure 3.1 Reset Sequence............................................................................................................ 58 Figure 3.2 Stack Status after Exception Handling ........................................................................ 60 Figure 3.3 Interrupt Sequence....................................................................................................... 61 Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62 Section 4 Address Break Figure 4.1 Block Diagram of Address Break................................................................................ 63 Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 66 Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 67 |
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