SH7615 datasheet(13/925 Pages) RENESAS

13 / 925 page

Rev. 2.00, 03/05, page xiii of xxxviii

Item

Page

Revisions (See Manual for Details)

7.5.3 Burst Reads

Figure 7.19 (a) Basic

Burst Read Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.20 (a) Burst

Read Wait Specification

Timing (Auto-Precharge)

Except tEcyc:tPcyc 1:1

Figure 7.21 (a) Single

Read Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.23 (a) Basic

Burst Write Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.24 (a) Burst

Read Timing (No

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.25 (a) Burst

Read Timing (Bank

Active, Same Row

Address)

Except tEcyc:tPcyc 1:1

Figure 7.26 (a) Burst

Read Timing (Bank

Active, Different Row

Addresses)

Except tEcyc:tPcyc 1:1

297,

299,

302,

305,

308,

310,

312

Figure title amended

7.5.11 64-Mbit

Synchronous DRAM (2

Mword × 32 Bit)

Connection

323

Synchronous DRAM Mode Settings

Description amended

Synchronous DRAM Mode Settings: To make mode settings

for the synchronous DRAM, write to address X + H'FFFF0000

or X + H'FFFF8000 from the CPU. (X represents the setting

value.) Whether to use X + H'FFFF0000 or X + H'FFFF8000

determines on the synchronous DRAM used.

Figure 7.35 128-Mbit

Synchronous DRAM (4

Mwords

× 32 Bits)

Connection Example

324

• 128-Mbit Synchronous DRAM (4 Mwords

× 32 Bits)

Connection Example

Figure 7.35 added

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