H8SXSLASH1657C datasheet(13/892 Pages) RENESAS

13 / 892 page

Rev. 2.00 Jun. 28, 2007 Page xiii of xxiv

6.7

Byte Control SRAM Interface ........................................................................................... 188

6.7.1

Byte Control SRAM Space Setting....................................................................... 188

6.7.2

Data Bus................................................................................................................ 188

6.7.3

I/O Pins Used for Byte Control SRAM Interface ................................................. 189

6.7.4

Basic Timing......................................................................................................... 190

6.7.5

Wait Control ......................................................................................................... 192

6.7.6

Read Strobe (

RD).................................................................................................. 194

6.7.7

Extension of Chip Select (

CS) Assertion Period................................................... 194

6.7.8

DACK Signal Output Timing ............................................................................... 195

6.8

Burst ROM Interface.......................................................................................................... 196

6.8.1

Burst ROM Space Setting..................................................................................... 196

6.8.2

Data Bus................................................................................................................ 196

6.8.3

I/O Pins Used for Burst ROM Interface................................................................ 197

6.8.4

Basic Timing......................................................................................................... 198

6.8.5

Wait Control ......................................................................................................... 200

6.8.6

Read Strobe (

RD) Timing..................................................................................... 200

6.8.7

Extension of Chip Select (

CS) Assertion Period................................................... 200

6.9

Address/Data Multiplexed I/O Interface ............................................................................ 201

6.9.1

Address/Data Multiplexed I/O Space Setting ....................................................... 201

6.9.2

Address/Data Multiplex ........................................................................................ 201

6.9.3

Data Bus................................................................................................................ 201

6.9.4

I/O Pins Used for Address/Data Multiplexed I/O Interface .................................. 202

6.9.5

Basic Timing......................................................................................................... 203

6.9.6

Address Cycle Control.......................................................................................... 205

6.9.7

Wait Control ......................................................................................................... 206

6.9.8

Read Strobe (

RD) Timing..................................................................................... 206

6.9.9

Extension of Chip Select (

CS) Assertion Period................................................... 208

6.9.10

DACK Signal Output Timing ............................................................................... 210

6.10

Idle Cycle........................................................................................................................... 211

6.10.1 Operation .............................................................................................................. 211

6.10.2 Pin States in Idle Cycle ......................................................................................... 220

6.11

Bus Release........................................................................................................................ 221

6.11.1 Operation .............................................................................................................. 221

6.11.2 Pin States in External Bus Released State............................................................. 222

6.11.3 Transition Timing ................................................................................................. 223

6.12

Internal Bus........................................................................................................................ 224

6.12.1 Access to Internal Address Space ......................................................................... 224

6.13

Write Data Buffer Function ............................................................................................... 225

6.13.1 Write Data Buffer Function for External Data Bus............................................... 225

6.13.2 Write Data Buffer Function for Peripheral Modules ............................................ 226

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