H8SXSLASH1658R datasheet(13/1374 Pages) RENESAS

13 / 1374 page

Rev. 2.00 Sep. 25, 2008 Page xiii of xxx

8.3.2

Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 169

8.3.3

Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 170

8.4

Operation .......................................................................................................................... 172

8.4.1

Setting of Break Control Conditions................................................................. 172

8.4.2

PC Break ........................................................................................................... 172

8.4.3

Condition Match Flag ....................................................................................... 173

8.5

Usage Notes ...................................................................................................................... 174

Section 9 Bus Controller (BSC).........................................................................177

9.1

Features............................................................................................................................. 177

9.2

Register Descriptions ........................................................................................................ 180

9.2.1

Bus Width Control Register (ABWCR)............................................................ 181

9.2.2

Access State Control Register (ASTCR) .......................................................... 182

9.2.3

Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 183

9.2.4

Read Strobe Timing Control Register (RDNCR) ............................................. 188

9.2.5

CS Assertion Period Control Registers (CSACR) ............................................ 189

9.2.6

Idle Control Register (IDLCR) ......................................................................... 192

9.2.7

Bus Control Register 1 (BCR1) ........................................................................ 194

9.2.8

Bus Control Register 2 (BCR2) ........................................................................ 196

9.2.9

Endian Control Register (ENDIANCR)............................................................ 197

9.2.10

SRAM Mode Control Register (SRAMCR) ..................................................... 198

9.2.11

Burst ROM Interface Control Register (BROMCR)......................................... 199

9.2.12

Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 201

9.3

Bus Configuration............................................................................................................. 202

9.4

Multi-Clock Function and Number of Access Cycles ...................................................... 203

9.5

External Bus...................................................................................................................... 207

9.5.1

Input/Output Pins .............................................................................................. 207

9.5.2

Area Division.................................................................................................... 210

9.5.3

Chip Select Signals ........................................................................................... 211

9.5.4

External Bus Interface....................................................................................... 212

9.5.5

Area and External Bus Interface ....................................................................... 216

9.5.6

Endian and Data Alignment.............................................................................. 221

9.6

Basic Bus Interface ........................................................................................................... 224

9.6.1

Data Bus............................................................................................................ 224

9.6.2

I/O Pins Used for Basic Bus Interface .............................................................. 224

9.6.3

Basic Timing..................................................................................................... 225

9.6.4

Wait Control ..................................................................................................... 231

9.6.5

Read Strobe (

RD) Timing................................................................................. 233

9.6.6

Extension of Chip Select (

CS) Assertion Period............................................... 234

9.6.7

DACK and EDACK Signal Output Timings .................................................... 236

H8SX/1658R Datasheet(PDF) 13 Page - Renesas Technology Corp

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