M16CSLASH29 datasheet(341/499 Pages) RENESAS

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19. Programmable I/O Ports

page 317

19.5 Pin Assignment Control Register (PACR)

Figure 19.10

shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before

a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function

as I/O ports.

Bits PACR2 to PACR0: control pins to be used

Value after reset: 0002.

To select the 80-pin package, set the bits to 0112.

To select the 64-pin package, set the bits to 0102.

U1MAP bit: controls pin assignments for the UART1 function.

_________ _________

To assign the UART1 function to P64/CTS1/RTS1, P65/CLK1, P66/RxD1, and P67/TxD1, set the U1MAP

bit to 0 (P67 to P64).

________ ________

To assign the function to P70/CTS1/RTS1, P71/CLK1, P72/RxD1, and P73/TxD1, set the U1MAP bit to 1

(P73 to P70)

The PRC2 bit in the PRCR protects the PACR register. Set the PACR register after setting the PRC2 bit in

the PRCR register.

19.6 Digital Debounce Function

Two digital debounce function circuits are provided. Level is determined when level is held, after applying

either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables

noise reduction.

________

_______ _____

This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and

the P17DDR register respectively. Figure 19.11 shows the NDDR register and the P17DDR register.

Additionally, a digital debounce function is disabled to the port P17 input and the port P85 input.

Filter width : (n+1) x 1/f8

n: count value set in the NDDR register and P17DDR register

The NDDR register and the P17DDR register decrement count value with f8 as the count source. The

NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or a

rising edge is applied to the pin.

The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce

function. Setting to FF16 disables the digital filter. See Figure 19.12 for details.

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