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M16C/29 Datasheet(PDF) 61 Page - Renesas Technology Corp |
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M16C/29 Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 499 page  5. Resets p u o r G 9 2 / C 6 1 M page 37 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Status Pin name P0 to P3, P6 to P10 Input port (high impedance) Figure 5.3 CPU Register Status After Reset b15 b0 Data register(R0) Address register(A0) Frame base register(FB) Program counter(PC) Interrupt table register(INTB) User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB) Flag register(FLG) 000016 000016 000016 C D Z S B O I U IPL 000016 000016 000016 000016 000016 b19 b0 Content of addresses FFFFE16 to FFFFC16 b15 b0 b15 b0 b15 b0 b7 b8 0000016 Data register(R1) Data register(R2) Data register(R3) Address register(A1) 000016 000016 000016 Figure 5.2 Reset Sequence td(P-R) More than td(ROC) CPU clock Address ROC RESET Content of reset vector CPU clock: 28 cycles FFFFE16 FFFFC16 VCC Max. 2 ms |
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