M16CSLASH29 datasheet(121/499 Pages) RENESAS

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11. DMAC

page 97

Figure 11.5 Transfer Cycles for Source Read

CPU clock

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(3) When the source read cycle under condition (1) has one wait state inserted

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address.

Address

bus

RD signal

WR signal

Data

bus

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(4) When the source read cycle under condition (2) has one wait state inserted

NOTE:

1. The same timing changes occur with the respective conditions at the destination as at the source.

CPU clock

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