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M16C/29 Datasheet(PDF) 208 Page - Renesas Technology Corp |
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M16C/29 Datasheet(HTML) 208 Page - Renesas Technology Corp |
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208 / 499 page  14.Serial I/O p u o r G 9 2 / C 6 1 M page 184 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. •Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to 0 (reception disabled) (2) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled) (3) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode) (4) Set the RE bit in the UiC1 register to 1 (reception enabled) •Resetting the UiTB register (i=0 to 2) (1) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled) (2) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode) (3) 1 is written to TE bit in the UiC1 register (reception enabled), regardless to the TE bit. |
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