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M16C/29 Datasheet(PDF) 276 Page - Renesas Technology Corp |
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M16C/29 Datasheet(HTML) 276 Page - Renesas Technology Corp |
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276 / 499 page  15. A/D Converter p u o r G 9 2 / C 6 1 M page 252 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 15.28 ADTRGCON Register in Delayed Trigger Mode 1 Table 15.13 Trigger Select Bit Setting in Delayed Trigger Mode 1 Trigger TRG 0 HPTRG0 0 TRG1 1 ADTRG HPTRG1 0 A/D Trigger Control Register (1) Symbol Address After Reset ADTRGCON 03D216 0016 Bit Name Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D operation mode select bit 2 SSE AN0 trigger select bit See Table 15.13 HPTRG1 AN1 trigger select bit HPTRG0 RW RW RW RW RW See Table 15.13 Nothing is assigned. If necessary, set to 0. When read, the content is 0 (b7-b4) NOTE: 1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be undefined. DTE 1 01 Simultaneous sample sweep mode or delayed trigger mode 0, 1 A/D operation mode select bit 3 Delayed trigger mode 0, 1 0 |
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