HD6432351 datasheet(387/1025 Pages) RENESAS

387 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 353 of 988

REJ09B0330-0300

Port 3 Register (PORT3)

—

Undefined

—

Undefined

—

P35

—*

P34

—*

P33

—*

P30

—*

P32

—*

P31

—*

Bit

Initial value

R/W

Note: * Determined by state of pins P35 to P30.

PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3

pins (P35 to P30) must always be performed on P3DR.

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.

If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3

read is performed while P3DDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin

states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and

in software standby mode.

Port 3 Open Drain Control Register (P3ODR)

—

Undefined

—

Undefined

—

P35ODR

R/W

P34ODR

R/W

P33ODR

R/W

P30ODR

R/W

P32ODR

R/W

P31ODR

R/W

Bit

Initial value

R/W

P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3

pin (P35 to P30).

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.

Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin,

while clearing the bit to 0 makes the pin a CMOS output pin.

P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

HD6432351 Datasheet(PDF) 387 Page - Renesas Technology Corp

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