HD6432351 datasheet(402/1025 Pages) RENESAS

402 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 368 of 988

REJ09B0330-0300

9.8.2

Table 9.13 shows the port A register configuration.

Table 9.13 Port A Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port A data direction register

PADDR

H'00

H'FEB9

Port A data register

PADR

R/W

H'00

H'FF69

Port A register

PORTA

Undefined

H'FF59

Port A MOS pull-up control register*

2 PAPCR

R/W

H'00

H'FF70

Port A open-drain control register*

PAODR

R/W

H'00

H'FF77

Notes: 1. Lower 16 bits of the address.

2. Only applies to the H8S/2351.

Port A Data Direction Register (PADDR)

PA7DDR

PA6DDR

PA5DDR

PA4DDR

PA3DDR

PA0DDR

PA2DDR

PA1DDR

Bit

Initial value

R/W

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A. PADDR cannot be read; if it is, an undefined value will be read.

PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to

select whether the address output pins retain their output state or become high-impedance when a

transition is made to software standby mode.

• Modes 1 to 3, and 7*

Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing

the bit to 0 makes the pin an input port.

• Modes 4 and 5

The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to

PA0DDR.

Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address

output, while clearing the bit to 0 makes the pin an input port.

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