HD6432351 datasheet(410/1025 Pages) RENESAS

410 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 376 of 988

REJ09B0330-0300

9.9.2

Table 9.15 shows the port B register configuration.

Table 9.15 Port B Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port B data direction register

PBDDR

H'00

H'FEBA

Port B data register

PBDR

R/W

H'00

H'FF6A

Port B register

PORTB

Undefined

H'FF5A

Port B MOS pull-up control register

PBPCR

R/W

H'00

H'FF71

Note:

* Lower 16 bits of the address.

Port B Data Direction Register (PBDDR) [H8S/2351 Only]

PB7DDR

PB6DDR

PB5DDR

PB4DDR

PB3DDR

PB0DDR

PB2DDR

PB1DDR

Bit

Initial value

R/W

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.

PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to

select whether the address output pins retain their output state or become high-impedance when a

transition is made to software standby mode.

• Modes 1, 4, and 5

The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.

• Modes 2 and 6

Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while

clearing the bit to 0 makes the pin an input port.

• Modes 3 and 7

Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing

the bit to 0 makes the pin an input port.

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