HD6432351 datasheet(440/1025 Pages) RENESAS

440 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 406 of 988

REJ09B0330-0300

9.14.2

Table 9.25 shows the port G register configuration.

Table 9.25 Port G Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port G data direction register

PGDDR

H'10/H'00*

H'FEBF

Port G data register

PGDR

R/W

H'00

H'FF6F

Port G register

PORTG

Undefined

H'FF5F

Notes: 1. Lower 16 bits of the address.

2. Value of bits 4 to 0.

3. Initial value depends on the mode.

Port G Data Direction Register (PGDDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PG4DDR

PG3DDR

PG0DDR

PG2DDR

PG1DDR

Bit

Modes 1, 4, 5

Initial value

R/W

Modes 2, 3, 6, 7

Initial value

R/W

PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an

undefined value will be read.

The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes

1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in

software standby mode. The OPE bit in SBYCR is used to select whether the bus control output

pins retain their output state or become high-impedance when a transition is made to software

standby mode.

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