HD6432351 datasheet(469/1025 Pages) RENESAS

469 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 435 of 988

REJ09B0330-0300

Channel

Bit 3

IOC3

Bit 2

IOC2

Bit 1

IOC1

Bit 0

IOC0 Description

Output disabled

(Initial value)

0 output at compare match

1 output at compare match

TGR0C

is output

compare

Initial output is 0

output

Toggle output at compare

match

Output disabled

0 output at compare match

1 output at compare match

Initial output is 1

output

Toggle output at compare

match

Input capture at rising edge

Input capture at falling edge

Capture input

source is

TIOCC0 pin

Input capture at both edges

TGR0C

is input

capture

Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down

Legend: *: Don’t care

Note:

1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

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