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HD6432351 Datasheet(PDF) 477 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 477 Page - Renesas Technology Corp |
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477 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 443 of 988 REJ09B0330-0300 10.2.5 Timer Status Register (TSR) 7 — 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 0 TGFA 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* Bit Initial value R/W Note: * Can only be written with 0 for flag clearing. : : : Channel 0: TSR0 Channel 3: TSR3 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 0 TGFA 0 R/(W)* 2 — 0 — 1 TGFB 0 R/(W)* Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit Initial value R/W Note: * Can only be written with 0 for flag clearing. : : : The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. |
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