HD6432351 datasheet(547/1025 Pages) RENESAS

547 / 1025 page

Section 11 Programmable Pulse Generator (PPG)

Rev. 3.00 Sep 15, 2006 page 513 of 988

REJ09B0330-0300

Different Triggers for Pulse Output Groups

If pulse output groups 2 and 3 are triggered by different compare match events, the address of the

upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is

H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that

cannot be modified and are always read as 1.

• Address H'FF4C

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

—

Bit

Initial value

R/W

• Address H'FF4E

—

NDR11

R/W

NDR8

R/W

NDR10

R/W

NDR9

R/W

Bit

Initial value

R/W

If pulse output groups 0 and 1 are triggered by different compare match event, the address of the

upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F.

Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be

modified and are always read as 1.

• Address H'FF4D

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

—

Bit

Initial value

R/W

• Address H'FF4F

—

NDR3

R/W

NDR0

R/W

NDR2

R/W

NDR1

R/W

Bit

Initial value

R/W

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