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HD6432351 Datasheet(PDF) 665 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 665 Page - Renesas Technology Corp |
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665 / 1025 page  Section 14 Smart Card Interface Rev. 3.00 Sep 15, 2006 page 631 of 988 REJ09B0330-0300 (1) Data write TDR TSR (shift register) Data 1 (2) Transfer from TDR to TSR Data 1 Data 1 ; Data remains in TDR (3) Serial data output Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set I/O signal line output Data 1 Data 1 Figure 14.5 Relation Between Transmit Operation and Internal Registers Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I/O data 12.5etu TXI (TEND interrupt) 11.0etu DE Guard time When GM = 1 Legend: Ds : Start bit D0 to D7 : Data bits Dp : Parity bit DE : Error signal When GM = 0 Figure 14.6 TEND Flag Generation Timing in Transmission Operation |
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