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HD6432351 Datasheet(PDF) 690 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 690 Page - Renesas Technology Corp |
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690 / 1025 page ![]() Section 15 A/D Converter Rev. 3.00 Sep 15, 2006 page 656 of 988 REJ09B0330-0300 Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conversion start delay tD 10 — 17 6 — 9 Input sampling time tSPL — 63 — — 31 — A/D conversion time tCONV 259 — 266 131 — 134 Note: Values in the table are the number of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 15.6 shows the timing. φ ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing |
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