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HD6432351 Datasheet(PDF) 860 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 860 Page - Renesas Technology Corp |
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860 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 826 of 988 REJ09B0330-0300 TMDR4—Timer Mode Register 4 H'FE91 TPU4 0 1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — Mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * Note: 7 — 1 — 6 — 1 — 5 — 0 — 4 — 0 — 3 MD3 0 R/W 0 MD0 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W Bit Initial value Read/Write : : : MD3 is a reserved bit. In a write, it should always be written with 0. Legend: *: Don’t care |
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