HD6432351 datasheet(869/1025 Pages) RENESAS

869 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 835 of 988

REJ09B0330-0300

TSR5—Timer Status Register 5

H'FEA5

TPU5

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

Read/Write

TCNT counts down

TCNT counts up

Count Direction Flag

Underflow Flag

Overflow Flag

Input Capture/Output Compare Flag B

[Clearing conditions]

• When DTC is activated by TGIA interrupt while

DISEL bit of MRB in DTC is 0

• When DMAC is activated by TGIA interrupt while

DTA bit of DMABCR in DMAC is 1

• When 0 is written to TGFA after reading TGFA = 1

Input Capture/Output Compare Flag A

[Setting conditions]

• When TCNT = TGRA while TGRA is functioning

as output compare register

• When TCNT value is transferred to TGRA by

input capture signal while TGRA is functioning

as input capture register

Note: * Can only be written with 0 for flag clearing.

[Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL

bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning as

output compare register

• When TCNT value is transferred to TGRB by input

capture signal while TGRB is functioning as input

capture register

[Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

[Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

[Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

[Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

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