HD6432351 datasheet(120/1025 Pages) RENESAS

120 / 1025 page

Section 4 Exception Handling

Rev. 3.00 Sep 15, 2006 page 86 of 988

REJ09B0330-0300

4.4

Interrupts

Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and

42 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources

and the number of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

refresh timer, 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer

controller (DTC), DMA controller (DMAC), and A/D converter. Each interrupt source has a

separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI to

eight priority/mask levels to enable multiplexed interrupt control.

For details of interrupts, see section 5, Interrupt Controller.

Interrupts

External

interrupts

Internal

interrupts

NMI (1)

IRQ7 to IRQ0 (8)

WDT*1 (1)

Refresh timer*2 (1)

TPU (26)

SCI (8)

DTC (1)

DMAC (4)

A/D converter (1)

Numbers in parentheses are the numbers of interrupt sources.

1. When the watchdog timer is used as an interval timer, it generates

an interrupt request at each counter overflow.

2. When the refresh timer is used as an interval timer, it generates an

interrupt request at each compare match.

Notes:

Figure 4.4 Interrupt Sources and Number of Interrupts

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